ESD Protection Strategy for Sub-Quarter-Micron CMOS Technology : Gate-driven Design Versus Substrate-triggered Design

The operation principles of gate-driven design and substratetriggered design for ESD (ElectroStatic Discharge) protection are first explained by energy-band diagrams in this paper. The onchip ESD protection devices realized in 0.18-μm and 0.35-μm CMOS processes are used to verify the efficiency of gate-driven or substrate-triggered designs. The substrate-triggered design can effectively and continually improve ESD robustness of protection devices than the gate-driven design. The HBM (Human-BodyModel) ESD level of NMOS with a W/L of 300μm/0.3μm can be improved from the original 0.8kV to become 3.3kV by the substrate-triggered design. But, the gate-driven design cannot continually improve the ESD level of the same device in the subquarter-micron CMOS process. INTRODUCTION ESD level of commercial IC products is generally requested to be higher than 2kV in the HBM [1] ESD stress. Therefore, onchip ESD protection circuits had been built on the chip to protect the devices and circuits against ESD damages. To sustain the requested ESD level without causing damage in IC, on-chip ESD protection circuits are often drawn with larger device dimensions. Such ESD protection devices in ESD protection circuits are often realized by finger-type layout to save total layout area [2]. But, during the ESD stress, the multiple fingers of ESD protection NMOS cannot be uniformly turned on. Only several fingers of the NMOS were turned on and therefore damaged by ESD [3]. The EMMI photography of turned-on NMOS (W/L=300μm/0.5μm) with 40mA drain pulse current is shown in Fig. 1. Only some regions of the center fingers in this NMOS are turned on. Due to the short-channel NMOS has the snapback effect on its I-V curve, as shown in Fig. 2. The turned-on center fingers of Fig. 1 will cause the ESD current crowding on those fingers. If the turned-on region cannot be extended to full regions of all fingers before second breakdown occurs in NMOS, the ESD current will be mainly discharged through this turned-on region. This often causes a low ESD level, even if the NMOS has a large device dimension. To improve the turn-on uniformity among the multiple fingers, the gate-driven design [3]-[5] and substrate-triggered design [6][8] had been reported to increase ESD level of the large-devicedimension NMOS. The design diagrams are summarized in Fig. 3(a) and 3(b), respectively. In Fig. 3(a), an ESD detection circuit is connected between the pad and the gate of NMOS. In Fig. 3(b), the ESD detection circuit is also connected between the pad and the bulk of NMOS. In normal operation condition, the VG in Fig. 3(a) must be kept at zero to turn off the channel of NMOS. The VB in Fig. 3(b) must be kept at ground to turn off the parasitic lateral BJT of NMOS. There are two current flow paths in protection devices during ESD stress. One is the channel current of MOSFET, the other is the turn-on current of parasitic lateral BJT. The gate-driven design often enhances the channel current during ESD stress, but there is almost no channel current in substrate-triggered design. The substrate-triggered design only improves the turn-on current of parasitic lateral BJT. Some discussion will be explained in the next section. Recently, ESD level of the gate-driven NMOS had been found to be decreased dramatically when the gate voltage is somewhat increased [5], [6], [9]. The gate-driven design causes ESD current flowing through the surface channel of NMOS, therefore NMOS becomes more sensitive to be burned out by ESD energy. With gate-driven design, the larger ESD current flowing on the surface channel can easily damage the interface between gate-oxide and substrate. However, the parasitic lateral BJT of MOSFET can sustain higher ESD current than the channel surface of MOSFET. If the lateral BJT can be controlled as the dominant ESD current path, the substrate-triggered design can sustain higher ESD current. In this paper, the operation principles of the gate-driven and substrate-triggered designs for ESD protection are clearly explicated by using energy-band diagrams. Fig. 1. The EMMI photography of turned-on NMOS (W/L = 300μm/0.5μm) with 40mA drain pulse current. Fig. 2. The snapback I-V curve of NMOS device with W/L of 300μm/0.5μm.